A low drop-out (LDO) voltage regulator is a regulator circuit that provides a well-specified and stable DC voltage (whose input-to-output voltage difference is typically low). The operation of the circuit is based on feeding back an amplified error signal, which is used to control output current flow of a ‘pass’ device (such as a power transistor) driving a load. The drop-out voltage is the value of the input/output differential voltage where regulation is lost.
The low drop-out nature of the regulator makes it more appropriate, in contrast to other types of regulators such as dc-dc converters and switching regulators, for use in many applications, such as automotive, portable, and industrial applications. In the automotive industry, a low drop-out voltage is necessary during cold-crank conditions, where an automobile's battery voltage can fall below 6V. Increasing demand for LDO voltage regulators is also apparent in mobile battery operated products (such as cellular phones, pagers, camera recorders and laptop computers), where the LDO voltage regulator typically needs to regulate under low voltage conditions with a reduced voltage drop.
A known LDO voltage regulator uses a differential transistor pair, an intermediate stage transistor, and a pass device coupled to a large (external) bypass capacitor. These elements constitute a DC regulation loop that provides voltage regulation.
In the field of voltage regulators, there is no voltage regulator currently available on the market that provides an efficient, high-performance voltage regulation over a wide range of possible loads, whilst maintaining an ultra-low bias current that ensures minimum current consumption in standby mode (i.e. when there is no load).
In this regard, the strategy adopted by all manufacturers, consists of making a performance versus consumption trade-off. Thus, the regulator performance suffers from either:                (i) The transient performance of the voltage regulator is poor, if it is operating at a relatively low current (Icc) for all loads; or        (ii) The regulator is likely operating inefficiently, if the voltage regulator is operating with a relatively high current (Icc) for all possible loads.        
Referring now to FIG. 1, a classic voltage regulator topology 100 is illustrated. The classic topology 100 comprises a 3-stage Amplifier, where:                (i) A first stage 110 of the voltage regulator operates as a differential pair of transistors with an active load;        (ii) A second stage 120 is a buffer stage with pole tracking; and        (iii) A third stage 130 is a ‘pass’ device 135 driving the load current.        
An external capacitance 140 is provided to provide fast buffering to accommodate load changes. In addition, a pair of resistors 150 is provided in parallel to the external capacitance 140, where the resistor ratio defines the output voltage (Vout); in this case 2×VREF. A minimum current is fixed through these feedback resistors and the output ‘pass’ device 135 to ensure the loop is stable (i.e. the open loop gain is limited).
Of note is the typical current drawn (Icc) per stage:
(i)first stage of approximately ~15 uA;(ii)second stage of approximately ~2 uA; and(iii)third stage of approximately~2-4 uA
This results in a total quiescent current drawn of approximately ˜20 uA, notably without a load. Thus, the inventors of the present invention have recognized and appreciated that an improved voltage regulator arrangement is needed to reduce this high current consumption value, particularly when such a current level is not required by the load.
To appreciate the problems associated with the classic topology of FIG. 1, it is worth considering the corresponding pole tracking plot 200 of the classic voltage regulator circuit, as illustrated in FIG. 2. Here, the voltage regulator is shown with 3-poles and 1-zero to ensure stability.
The pole tracking 200 is illustrated for both low loads 210 and high loads 220 of the voltage regulator. A first pole 230 for both loads is shown due to the output stage, where:
                              f          OUT                =                                            g                              m                ⁢                                                                  ⁢                7                                      ·                          (                                                r                                      DS                    ⁢                                                                                  ⁢                    7                                                  //                                  R                  L                                            )                                ⁢                      1                          1              +                              jω                ⁢                                                                  ⁢                                  C                  ⁡                                      (                                                                  r                                                  DS                          ⁢                                                                                                          ⁢                          7                                                                    //                                              R                        L                                                              )                                                                                                          [        1        ]            
Here, the gain of output stage changes with Load current
                                          g                          m              ⁢                                                          ⁢              7                                ·                      (                                          r                                  DS                  ⁢                                                                          ⁢                  7                                            //                              R                L                                      )                          ∝                  1                      I                                              [        2        ]            
Furthermore, the first pole 230 of the output stage is shown as changing with load current:
                              r                      DS            ⁢                                                  ⁢            7                          //                              R            L                    ∝                      1                          I              L                                                          [        3        ]            
A zero 240 results from the equivalent series resistance (ESR). A second pole 250 is illustrated, which is due to the differential pair of transistor arrangement. A third pole 260 is illustrated as a result of the buffering circuit.
Thus, as can be readily appreciated, increasing the load results in the following circuit changes:                (i) The Pole increases faster;        (ii) The Gain decreases 270; and        (iii) There is more remaining gain at higher frequencies, which is highly undesirable.        
Thus, there exists a need in the field of voltage regulators to optimise current efficiency, thereby improving battery life when the voltage regulator is used in a portable product, such as a mobile phone. In particular, the improvement in efficiency needs to be provided without any loss in performance or significant additional die size.